1. Field of the Invention
The present invention relates to a delay clock generating apparatus which generates a delay clock, and more particularly to a delay clock generating apparatus which is incorporated in a delay signal generator of a semiconductor testing device, which tests a semiconductor device.
2. Description of the Related Art
Recently, it has been necessary for a semiconductor testing device for testing a semiconductor device to control extremely high-speed operational timings, due to developments of semiconductor devices which operate at high-speed. It has been especially necessary that the semiconductor testing device delay timing with respect to a standard clock, for inputting a test pattern to a device under test (DUT), by an accurate delay time, in accordance with an input characteristic of the DUT.
FIG. 1 is a block diagram showing a delay line 176 in the semiconductor testing device, generating a delay indicator signal which is delayed by a predetermined time. The delay line 176 includes delay elements 180, 184, 188 and 192, selectors 182, 186, 190 and 194, and a memory 196. In this delay line 176, a clock is input to an input terminal and the delay indicator signal, which is delayed by a predetermined time with respect to the input clock, is output from an output terminal.
The memory 196 stores data in predetermined addresses, of combinations of the delay elements generating a predetermined delay time. Each of the selectors 182, 186, 190 and 194 selects either of the clocks, one of which is passed through each of the delay elements 180, 184, 188 and 192 and the other of which is not passed through each of the delay elements 180, 184, 188 and 192, and outputs the selected clock. For example, when the delay element 182 uses the delay element 180 in order to generate a predetermined delay time, xe2x80x9c0xe2x80x9d is stored in the corresponding bit of the memory 196. When, on the other hand, the delay element 182 does not use the delay element 180 in order to generated the predetermined delay time, xe2x80x9c1xe2x80x9d is stored in the corresponding bit of the memory 196.
Each of the delay elements 180, 184, 188 and 192 in the delay line 176 are set to have delay times of about several picoseconds, several tens of picoseconds, or several hundred picoseconds. Therefore, logically, three delay elements respectively having delay times of 10 picoseconds, 20 picoseconds, and 40 picoseconds should be provided, in order to set seven delay times of 10 picoseconds, 20 picoseconds, . . . , 70 picoseconds. The combinations of the three delay elements provide the seven delay times.
However, actually, errors occur between the actual delay time provided by the delay elements and the set delay time, because the quality of the delay elements are not equal, and delay time provided by the delay elements varies depending on the ambient temperature. It is necessary to determine the optimum combination of the delay elements by measuring the delay time provided by the delay times, in order to give a predetermined delay time.
FIG. 2 is a block diagram of a conventional semiconductor testing device in which an output signal output from a waveform formatter 12, which is delayed with respect to a signal generated by a pattern generator 10, is measured. In this measurement, the pattern generator 10 supplies a standard clock 34 to a timing generator 14 and supplies a measurement signal 32 to the waveform formatter 12 for measuring the delay time. The timing generator 14 includes a plurality of the delay lines 176, shown in FIG. 1, and generates the delay indicator signal 36 which is delayed by a predetermined time with respect to the standard clock 34, based on the arbitrarily selected combinations of the delay elements. The delay indicator signal 36 is supplied to the waveform formatter 12. The waveform formatter 12 delays the measurement signal 32 based on the delay indicator signal 36 and outputs the delayed measurement signal 38 to the oscilloscope 16. The oscilloscope 16 measures the delay time generated by the arbitrarily selected combinations of the delay elements. The data for the combinations of the delay elements are stored in predetermined addresses of the memory 196, shown in FIG. 1.
Conventionally, the delay time generated by the combinations of each of the delay elements is measured by the oscilloscope 16. The combinations of the delay elements and the corresponding data of the delay times are stored in the memory 196. The delay elements which can generate a desired delay time are selected based on the data stored in the memory 196, in accordance with the input characteristic of the semiconductor device when testing the semiconductor device.
Using the conventional method of measuring delay times creates disadvantages, because the delay times are measured by the oscilloscope 16. The oscilloscope 16 cannot measure waveforms output from the waveform formatter 12 corresponding to a plurality of pins of the waveform formatter 12. Furthermore, the oscilloscope 16 cannot measure an accurate delay time when the delay time is very small, for example, approximately several picoseconds, or several tens of picoseconds.
Conventionally, it was difficult to measure an accurate delay time generated by a combination of the delay elements, by measuring a delay clock, because it was difficult to generate the delay clock having an accurate delay time.
Therefore, it is an object of the present invention to provide a delay time measuring apparatus and a method of measuring delay times, capable of accurately measuring delay times of a plurality of parallel set delay lines.
It is an object of the present invention to provide a method of setting a combination of delay clocks that can generate a predetermined delay time.
It is an object of the present invention to provide a delay clock generating apparatus capable of generating a delay clock having an accurate delay time.
It is further an object of the present invention to provide a delay clock generating apparatus and a method of measuring delay times, which overcomes the above issues in the related art. This object is achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
In order to solve the above-stated problem, the present invention provides a delay clock generating apparatus generating a delay clock which is delayed by a predetermined time with respect to a standard clock, comprising: an oscillator oscillating a shift clock having a same cycle as the standard clock; a pulse inserter generating a pulse to be inserted in a reference shift clock, at least either of an upward shift or a downward shift of the reference shift clock being synchronized with an upward shift or a downward shift of the shift clock, respectively, the pulse inserter inserting the pulse in the reference shift clock; and a phase-lock unit generating the delay clock delayed by the predetermined time with respect to the standard clock, by delaying a phase of the shift clock oscillated by the oscillator with respect to a phase of the standard clock based on a reference standard clock synchronizing the standard clock and having a same cycle as the reference shift clock, and the reference shift clock including the insert-pulse.
The delay clock generating apparatus may further comprise a phase comparator outputting the reference standard clock and the reference shift clock based on a phase difference between a synchronous shift clock synchronizing the shift clock and a synchronous standard clock synchronizing the standard clock and having a same cycle as the synchronous shift clock.
The phase comparator may output the reference standard clock and the reference shift clock such that a downward shift of the reference standard clock and a downward shift of the reference shift clock are matched with each other, based on the synchronous standard clock and the synchronous shift clock.
The pulse inserter may insert the pulse between a downward shift of the reference shift clock and a next upward shift of the reference shift clock.
The pulse inserter may insert the pulse to the reference shift clock such that the pulse is synchronized with the standard clock.
The delay clock generating apparatus may further comprise: a synchronous standard clock generator outputting the synchronous standard clock by frequency dividing the standard clock; and a synchronous shift clock generator outputting the synchronous shift clock by frequency dividing the shift clock such that the synchronous shift clock has a same cycle as the synchronous standard clock.
The delay clock generating apparatus may further comprise a phase controller, generating a phase control signal indicating a cycle to which the pulse is to be inserted among a plurality of cycles of the reference shift clock; and the pulse inserter may insert the pulse to the cycle of the reference shift clock indicated by the phase control signal.
The phase-lock unit may delay a phase of the shift clock oscillated by the oscillator, based on the number of the pulses inserted in the plurality of cycles of the reference shift clock.
The phase-lock unit may comprise: a subtractor outputting an averaged value of a subtraction result, obtained by subtracting an electric potential of pulses of the reference shift clock including the insert-pulse from an electric potential of pulses of the synchronous standard clock; and a pulse width adjuster, adjusting a pulse width of the reference shift clock including the insert-pulse such that the averaged value of the subtraction result by the subtractor becomes zero.
The oscillator may be a ring oscillator by which an oscillation frequency varies in accordance with a source voltage; and the pulse width adjuster adjusts a pulse width of the reference shift clock including the insert-pulse by adjusting the source voltage of the ring oscillator, based on the averaged value of the subtraction result by the subtractor.
The ring oscillator may be mounted on a single chip with a plurality of electronic circuits; and the delay clock generating apparatus may further comprise a source voltage unit, supplying the source voltage adjusted based on the averaged value of the subtraction result, to the plurality of the electronic circuits.
The oscillator may be a voltage control type oscillator by which an oscillation frequency varies based on a controlled voltage; and the pulse width adjuster adjusts a pulse width of the reference shift clock including the insert-pulse by adjusting the controlled voltage of the voltage control type oscillator, based on the averaged value of the subtraction result by the subtractor.
The phase controller may generate the phase control signal such that the pulse is diffusely inserted along a time series of the plurality of cycles in the reference shift clock.
The phase controller may comprise: a counter having M bits (M is a natural number) and increasing an output value based on the synchronous standard clock; a insert-pulse setting register having (M+1) bits and storing numbers of the pulses to be inserted; a plurality of change-point detectors each detecting a change-point of the bits of the counter; and a plurality of AND circuits each logically multiplying a register value corresponding to a (Mxe2x88x92n+1) th bit (n is a natural number) of the insert-pulse setting register and an output value of the change-point detector corresponding to a nth bit of the counter; and the phase controller may indicate cycles to which the pulse is to be inserted based on the logical multiplication of the AND circuit.
In order to solve the above-stated problem, the present invention further provides a method of measuring a delay time of a delay line, the delay line comprising an input terminal and an output terminal for a standard clock, the output terminal being connected to a data input of a flip-flop circuit operated by a delay clock having a predetermined delay time with respect to the standard clock, comprising: setting a constant delay time for the delay line; supplying the standard clock to the input terminal of the delay line for which the constant delay time is set; supplying a synchronous delay clock synchronizing the delay clock to a clock input of the flip-flop circuit; averaging output logic values output from the flip-flop circuit; and measuring the constant delay time of the delay line based on averaged output logic values.
The measuring step may judge that the constant delay time of the delay line is equal to the predetermined delay time of the delay clock when the averaged output logic value is almost 0.5.
In order to solve the above-stated problem, the present invention further provides a delay time measuring apparatus measuring a delay time of a delay line, comprising: delay clock generating means generating a delay clock having a predetermined delay time with respect to a standard clock; standard clock supplying means supplying the clock to the delay line; a timing comparator comparing an edge of a delay pulse which is obtained by delaying the standard clock by the delay line and an edge of a synchronous delay clock synchronizing the delay clock, and outputting the compared result as a logic value xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d; averaging means generating an averaged value of the compared result output from the timing comparator; and measuring means measuring a delay time of the delay line based on the averaged value generated by the averaging means.
The timing comparator may include a flip-flop circuit having a data input to which the delay pulse is input and a clock input to which the synchronous delay clock is input.
The measuring means may judge that the delay time of the delay line is equal to the predetermined delay time of the delay clock when the averaged value is almost 0.5.
This summary of the invention does not necessarily describe all essential features so that the invention may also be a sub-combination of these described features.